View KS57C5532_88291.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KS57C5532/P5532
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The KS57C5532/P5532 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The KS57P5532 is a microcontroller which has 32-kbyte one-time-programmable EPROM but its functions are same to KS57C5532. With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the KS57C5532/P5532 offers an excellent design solution for a wide variety of telecommunication applications. Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the KS57C5532/P5532's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
DEVELOPMENT SUPPORT
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard hex files that also contain program control data for SMDS compatibility.
1-1
PRODUCT OVERVIEW
KS57C5532/P5532
FEATURES SUMMARY
Memory * * 1 K x 4-bit RAM 32 K x 8-bit ROM Bit Sequential Carrier * Supports 8-bit serial data transfer in arbitrary format
55 I/O Pins * * * Input only: 4 pins I/O: 43 pins N-channel open-drain I/O (S/W): 8 pins
Interrupts * * * 3 external interrupt vectors 4 internal interrupt vectors 2 quasi-interrupts
Memory-Mapped I/O Structure * Data memory bank 15
Power-Down Modes * * * Idle: Only CPU clock stops Stop: Main system clock stops Subsystem clock stop mode
DTMF Generator * 16 dual-tone frequencies for tone dialing
Oscillation Sources 8-bit Basic Timer * * Programmable internal timer Watchdog timer * * * * * Crystal, ceramic for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 3.579545 MHz (typical) Subsystem clock frequency: 32.768 kHz (typical) CPU clock divider circuit (by 4, 8, or 64)
Two 8-bit Timer/Counters * * * * * Programmable interval timer External event counter function Timer/counters clock outputs to TCLO0 and TCLO1 pins External clock signal divider Serial I/O interface clock generator
Instruction Execution Times * * * 0.67, 1.33, 10.7 s at 6.0 MHz 1.12, 2.23, 17.88 s at 3.579545 MHz 122 s at 32.768 kHz
Watch Timer * * Time interval generation: 0.5 s, 3.9 ms at 32.768 kHz 4 frequency outputs to the BUZ pin
Operating Temperature * - 40 C to 85 C
Operating Voltage Range * * 1.8 V to 5.5 V (at 3 MHz) 2.7 V to 5.5 V (at 6 MHz)
8-bit Serial I/O Interface * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable
Package Types * 64 SDIP, 64 QFP
1-2
KS57C5532/P5532
PRODUCT OVERVIEW
BLOCK DIAGRAM
XIN
INT0, INT1, INT2 INT4
RESET
XOUT
Watch Timer
Basic Timer
Watch-Dog Timer
P0.0/SCK P0.1/SO P0.2/SI P0.3/BTCO
XTIN XTOUT I/O Port 0
8-BIT Timer/ Counter 0 8-BIT Timer/ Counter 1
P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7 P8.0-P8.3 P9.0-P9.3 P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 P13.0-P13.2
Interrupt Control Block
Clock
Stack Pointer Serial I/O Port Program Counter
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCLO0 P3.1/TCLO1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
I/O Port 6 I/O Port 7 I/O Port 8 I/O Port 9 I/O Port 10 I/O Port 11 I/O Port 12 I/O Port 13
Internal Interrupts
Input Port1
Instruction Decoder
Program Status Word
I/O Port 2
Arithmetic and Logic Unit
I/O Port 3 Flags I/O Port 4 I/O Port 5
1 K x 4-BIT Data Memory
32 K Byte Program Memory
DTMF Generator
DTMF
Figure 1-1. KS57C5532/P5532 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
KS57C5532/P5532
PIN ASSIGNMENTS
P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 P3.3 P3.2 TEST DTMF VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XIN XOUT
RESET
Figure 1-2. KS57C5532/P5532 Pin Assignment Diagrams
KS57C5532 (64-SDIP-750)
P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1
1-4
KS57C5532/P5532
PRODUCT OVERVIEW
P8.0 P9.3 P9.2 P9.1 P9.0 VSS P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0
52 53 54 55 56 57 58 59 60 61 62 63 64
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
KS57C5532 (64-QFP-1420F)
P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 VDD DTMF TEST P3.2 P3.3 P12.0
Figure 1-2. KS57C5532/P5532 Pin Assignment Diagrams (Continued)
P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1-5
PRODUCT OVERVIEW
KS57C5532/P5532
PIN DESCRIPTIONS
Table 1-1. KS57C5532/P5532 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test is possible. 4-bit pull-up resistors are assignable by software to port 1. Same as port 0. Number 15 (8) 14 (7) 13 (6) 12 (5) Share Pin SO SI BTCO
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
I
1 (61) 2 (60) 3 (59) 4 (58) 11 (4) 10 (3) 9 (2) 8 (1) 34 (27) 33 (26) 29 (22) 28 (21) 38-35 (31-28) 42-39 (35-32)
INT0 INT1 INT2 INT4 TCLO0 TCLO1 CLO BUZ TCL0 TCL1 SCLK (1) SDAT (1) -
I/O
I/O
Same as port 0.
I/O
4-bit I/O ports. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable to input pins and are automatically disable for output pins. N-channel open-drain or push-pull output can be selected by software. Port 4 and 5 can be paired to support 8-bit data transfer. 4-bit I/O ports. 1-bit or 4-bit read/write and test is possible. Port 6 pins are individually software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Ports 6 and 7 can be paired to enable 8-bit data transfer. Same as port 0. 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins.
P6.0-P6.3 P7.0-P7.3
I/O
51-48 (44-41) 55-52 (48-45)
KS0-KS3 KS4-KS7
P8.0-P8.3 P9.0-P9.3
I/O I/O
59-56 (52-49) 63-60 (56-53)
- -
NOTES 1. SCLK and SDAT are used for KS57P5532 only. 2. Parentheses indicate pin number for 64 QFP package.
1-6
KS57C5532/P5532
PRODUCT OVERVIEW
Table 1-1. KS57C5532/P5532 Pin Descriptions (Continued) Pin Name P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 I/O Pin Type I/O Description Same as port 9. Ports 10 and 11 can be paired to support 8-bit data transfer. 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-down resistors are software assignable; pull-down resistors are automatically disabled for output pins. 3-bit I/O port; characteristics are same as port 9. DTMF output. Serial I/O interface clock signal Serial data output Serial data input Basic timer clock output External interrupts. The triggering edge for INT0 and INT1 is selectable. INT0 is synchronized to system clock. Quasi-interrupt with detection of rising edges External interrupt with detection of rising and falling edges. Timer/counter 0 clock output Timer/counter 1 clock output Clock output 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the watch timer clock frequency of 32.768 kHz for buzzer sound External clock input for timer/counter 0 External clock input for timer/counter 1 Quasi-interrupt inputs with falling edge detection Number 19-16 (12-9) 23-20 (16-13) 27-24 (20-17) Share Pin -
-
P13.0-P13.2 DTMF SO SI BTCO INT0, INT1
I/O O I/O I/O I/O I/O I
7-5 (64-62) 31 (24) 15 (8) 14 (7) 13 (6) 12 (5) 4, 3 (61, 60) 2 (59) 1 (58) 11 (4) 10 (3) 9 (2) 8 (1)
- - P0.0 P0.1 P0.2 P0.3 P1.0, P1.1
INT2 INT4 TCLO0 TCLO1 CLO BUZ
I I I/O I/O I/O I/O
P1.2 P1.3 P2.0 P2.1 P2.2 P2.3
TCL0 TCL1 KS0-KS3 KS4-KS7
I/O I/O I/O
34 (27) 33 (26) 51-48 (44-41) 55-52 (48-45)
P3.0 P3.1 P6.0-P6.3 P7.0-P7.3
NOTE: Parentheses indicate pin number for 64 QFP package.
1-7
PRODUCT OVERVIEW
KS57C5532/P5532
Table 1-1. KS57C5532/P5532Pin Descriptions (Concluded) Pin Name VDD VSS XIN, XOUT Pin Type - - I - Power supply Ground Reset signal Crystal, ceramic, or R/C oscillator signal for main system clock. (For external clock input, use XIN and input XIN's reverse phase to XOUT) Crystal oscillator signal for subsystem clock. (For external clock input, use XTIN and input XTIN's reverse phase to XTOUT) Chip test input pin. Hold GND when the device is operating. Description Number 32 (25) 64 (57) 43 (36) 45, 44 (38, 37) 46, 47 (39, 40) 30 (23) Share Pin - - - -
XTIN, XTOUT
-
-
TEST
-
-
NOTE: Parentheses indicate pin number for 64 QFP package.
1-8
KS57C5532/P5532
PRODUCT OVERVIEW
Table 1-2. Overview of KS57C5532/P5532 Pin Data Pin Names P0.0-P0.3 P1.0-P1.3 P2.0-P2.3 P3.0-P3.1 P3.2-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.3 P8.0-P8.3 P9.0-P9.3 P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 P13.0-P13.2 DTMF XIN, XOUT XTIN, XTOUT NC VDD, VSS KS0-KS3 KS4-KS7 - - - - - - - - - - Share Pins , SO, SI, BTCO INT0, INT1, INT2, INT4 TCLO0, TCLO1, CLO, BUZ TCL0, TCL1 - - I/O Type I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O - I - - Reset Value Input Input Input Input Input Input Input Input Input Input Input Input High impedence - - - - Circuit Type D-4 A-1 D-2 D-4 D-2 E-2 D-4 D-2 D-2 D-2 D-6 D-2 G-6 - B - -
1-9
PRODUCT OVERVIEW
KS57C5532/P5532
PIN CIRCUIT DIAGRAMS
VDD
VDD Pull-Up Resistor
P-Channel In N-Channel
In
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD Pull-Up Resistor P-Channel In Pull-Up Resistor Enable Data
VDD
P-Channel Out
Output DIsable Schmitt Trigger
N-Channel
Figure 1-4. Pin Circuit Type A-1
Figure 1-6. Pin Circuit Type C
1-10
KS57C5532/P5532
PRODUCT OVERVIEW
VDD
Data Output DIsable
Circuit Type C
I/O
Pull-up Enable Data Output DIsable
P-Channel
Circuit Type C
I/O Pull-down Enable
Figure 1-7. Pin Circuit Type D-2
Figure 1-9. Pin Circuit Type D-6
VDD PNE Pull-up Enable Data Output Disable P-Channel Data Circuit Type C I/O
VDD
VDD
Pull-up Enable I/O
Output Disable
Schmitt Trigger
Figure 1-8. Pin Circuit Type D-4
Figure 1-10. Pin Circuit Type E-2
1-11
PRODUCT OVERVIEW
KS57C5532/P5532
DTMF Out + Disable
1-12
KS57C5532/P5532
ELECTRICAL DATA
14
OVERVIEW
-- I/O capacitance
ELECTRICAL DATA
In this section, information on KS57C5532 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- System clock oscillator characteristics -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN and XOUT -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
KS57C5532/P5532
Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL Conditions - All I/O ports - One I/O port active All I/O ports active Output Current Low One I/O port active Rating - 0.3 to 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15 (note) All I/O ports, total TA Tstg + 100 (Peak value) + 60 (note) Operating Temperature Storage Temperature - -
Duty . C C
Units V V V mA
mA
- 40 to + 85 - 65 to + 150
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 VIH4 Input Low Voltage VIL1 VIL2 VIL3 Conditions All input pins except those specified below for VIH2-VIH4 Ports 0, 1, 3, 6, 7, and RESET Ports 4 and 5 with pull-up resistors assigned XIN, XOUT and XTIN All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 3, 6, 7, and RESET XIN, XOUT and XTIN Min 0.7 VDD 0.8 VDD 0.7 VDD VDD - 0.1 - - Typ - Max VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 V Units V
14-2
KS57C5532/P5532
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output High Voltage Output Low Voltage Symbol VOH VOL1 Conditions IOH = - 1 mA Ports except 1 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4,5 only VDD = 1.8 to 5.5 V, IOL = 1.6mA VOL2 VDD = 4.5 V to 5.5 V IOL = 4mA all out Ports except ports 4,5 VDD = 1.8 to 5.5 V, IOL = 1.6mA Input High Leakage Current ILIH1 VI = VDD All input pins except those specified below for ILIH2 VI = VDD XIN, XOUT and XTIN Input Low Leakage Current ILIL1 VI = 0 V All input pins except below and RESET VI = 0 V XIN, XOUT and XTIN Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH VO = VDD All output pins VO = 0 V All output pins VDD = 5 V; VI = 0 V except RESET VDD = 3 V RL3
Pull-Down Resistor
Min VDD - 1.0 -
Typ - - -
Max - 2 0.4 2 0.4
Units V V V V V A
-
-
3
ILIH2
20 A
-
-
-3
ILIL2
- 20 A
-
-
3
ILOL
-
-
-3
RL1
25 50 100 200 25 50
45 89 212 441 46 95
100 200 400 800 100 200
k
VDD = 5 V; VI = 0 V; RESET VDD = 3 V VDD = 5 V; VI = VDD; Port 12 VDD = 3 V
RL4
14-3
ELECTRICAL DATA
KS57C5532/P5532
Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (DTMF ON) Conditions Run mode; VDD = 5.0 V 10% 3.58 MHz Crystal oscillator; C1 = C2 = 22 pF VDD = 3 V 10% IDD2 Run mode; VDD = 5.0 V 10% VDD = 3 V 10% IDD3 Idle mode; VDD = 5 V 10% VDD = 3 V 10% IDD4 IDD5 IDD6 Run mode; VDD = 3.0 V 10% 32 kHz Crystal oscillator Idle mode; VDD = 3.0 V 10% 32 kHz Crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Row Tone Level (2) Ratio of Column to Row Tone (2) Distortion (2) (Dual tone) VROW dBCR VDD = 2.0 V to 5.5 V RL =12 K; Temp = - 30 to 60 C VDD = 2.0 V to 5.5 V RL = 12 K; Temp = - 30 to 60 C VDD = 2.0 V to 5.5 V 1 MHz band, RL = 12 K Temp = - 30 to 60 C - 16 1 SCMOD = 0000B XT = 0V SCMOD = 0100B - 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz - 1.6 2.7 2.0 1.3 0.9 0.8 0.7 0.3 0.2 12.5 4.5 1.9 0.6 0.2 0.1 - 14 2 3.0 8.0 4.0 4.0 2.3 2.5 1.8 1.5 1.0 30 15 5 3 3 2 - 11 3 dBV dB A Min - Typ 3.0 Max 5.0 Units mA
(DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF
THD
-
-
5
%
NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. 3. DTMF electrical characteristics. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
14-4
KS57C5532/P5532
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter
Test Condition
Min 0.4
Typ -
Max 6.0
Units MHz
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator
XIN XOUT
0.4 - 0.4
- - -
3 4 6.0 ms MHz
VDD = 3 V
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock
XIN XOUT
0.4 - 0.4
- - -
3 10 6.0 ms MHz
VDD = 3 V VDD = 2.7 V to 5.5 V
XIN input frequency (1)
VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) -
0.4 83.3
- -
3 1250 ns
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.
14-5
ELECTRICAL DATA
KS57C5532/P5532
Table 14-4. Recommended Oscillator Constants (TA = - 40 C to + 85 C) Manufacturer Series Number (1) Frequency Range Load Cap (pF) C1 TDK FCR FCR CCR M5 MC5 MC3 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
14-6
KS57C5532/P5532
ELECTRICAL DATA
Table 14-5. Subsystem Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTI
N
Parameter Oscillation frequency (1)
Test Condition -
Min 32
Typ 32.76 8
Max 35
Units kHz
XTOUT
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V
- - 32
1.0 - -
2 10 100
s s kHz
External Clock
XTI XTOUT
N
XTIN input frequency (1)
-
XTIN input high and low level width (tXH, tXL)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is terminated.
Table 14-6. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
14-7
ELECTRICAL DATA
KS57C5532/P5532
Table 14-7. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (1) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0, TCL1 Input Frequency fTI0, fTI1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0, TCL1 Input High, Low Width tTIH0, tTIL0 tTIH1, tTIL1 tKCY VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Cycle Time VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
SCK High, Low
Min 0.67 1.33 0
Typ -
Max 64
Units s
-
1.5 1
MHz MHz s
0.48 1.8 800 670 3200 3800 335 tKCY-250 1600 tKCY-2150 100 150 150 500 400 400 600 500
-
-
-
-
ns
tKH, tKL
Width
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
-
-
ns
SI Setup Time to SCK High
tSIK
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
-
-
ns
SI Hold Time to SCK High
tKSI
VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
-
-
ns
14-8
KS57C5532/P5532
ELECTRICAL DATA
Table 14-7. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output Delay for SCK to SO Symbol tKSO
(note)
Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source
Min -
Typ -
Max 300 250 1000 1000
Units ns
Interrupt Input High, Low Width
RESET Input
tINTH, tINTL tRSL
INT0, INT1, INT2, INT4, KS0-KS7 Input
10 10
- -
- -
s s
Low Width
NOTE: R (1 k) and C (100 pF) are the load resistance and load capacitance of the SO output line.
CPU Clock 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 0.75 MHz
4.2 MHz 3 MHz
15.625 kHz 1 2 1.8 3 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) 4 5 6 7
Figure 14-1. Standard Operating Voltage Range
14-9
ELECTRICAL DATA
KS57C5532/P5532
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.5 V - Released by Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx
(2)
Max 5.5 10 - - -
Unit V A s ms ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-10
KS57C5532/P5532
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction
RESET
tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention
Normal Operating Mode
VDD
VDDDR Execution of STOP Instrction
tSREL
tWAIT Power-down Mode Terminating (Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-11
ELECTRICAL DATA
KS57C5532/P5532
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 14-5. Clock Timing Measurement at XIN (XTIN)
1/fTI tTIL tTIH
TCL
0.8 VDD 0.2 VDD
Figure 14-6. TCL0/1 Timing
14-12
KS57C5532/P5532
ELECTRICAL DATA
tRSL
RESET
0.2 VDD
Figure 14-7. Input Timing for
Signal
tINTL
tINTH
INT0, 1, 2, 4, KS0 to KS7
0.8 VDD 0.2 VDD
Figure 14-8. Input Timing for External Interrupts and Quasi-Interrupts
14-13
ELECTRICAL DATA
KS57C5532/P5532
tKCY tKL tKH
SCK
0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKS
O
SO
Output Data
Figure 14-9. Serial Data Transfer Timing
14-14
KS57C5532/P5532
MECHANICAL DATA
15
-- Pad diagram
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters
23.90 0.3 0-8 20.00
0.2 +0.10 -0.05
0.15
17.90 0.3
14.00 0.2
64-QFP-1420F
0.80 0.20
0.10 MAX
#64 (1.00) (1.00)
#1 1.00
0.40+0.10 -0.05 0.15 MAX
0.05-0.25 2.65 0.10 3.00 MAX
0.80 0.20 NOTE: Dimensions are in millimeters.
Figure 15-1. 64-QFP-1420F Package Dimensions
15-1
MECHANICAL DATA
KS57C5532/P5532
#64
#33
0-15
0.2
17.00
64-SDIP-750
19.05
#1
#32
57.80 0.2
NOTE:
Dimensions are in millimeters.
Figure 15-2. 64-SDIP-750C Package Dimensions
15-2
3.30
(1.34)
1.00 0.1
1.778
0.51 MIN
0.3
0.45 0.1
4.10 0.2
58.20 MAX
5.08 MAX
0.2 5
+0 - 0 .1 .05
KS57C5532/P5532
KS57P5532 OTP
16
OVERVIEW
KS57P5532OTP
The KS57P5532 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C5532 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS57P5532 is fully compatible with the KS57C5532, both in function and in pin configuration. Because of its simple programming requirements, the KS57P5532 is ideal for use as an evaluation chip for the KS57C5532.
16-1
KS57P5532 OTP
KS57C5532/P5532
P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 SDAT/P3.3 SCLK/P3.2 VPP/TEST DTMF VDD/VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS/VSS P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XIN XOUT
RESET/RESET
NOTE: The bold indicate a OTP pin name.
Figure 16-1. KS57P5532 Pin Assignments (64-SDIP)
KS57P5532 (64-SDIP-750)
P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1
16-2
KS57C5532/P5532
KS57P5532 OTP
RESET/ RESET
P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XIN XOUT P8.0 P9.3 P9.2 P9.1 P9.0 VSS/VSS P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 52 53 54 55 56 57 58 59 60 61 62 63 64
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
P5.0 P5.1 P5.2
KS57P5532 (64-QFP-1420F)
P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 VDD/VDD DTMF TEST/VPP P3.2/SCLK P3.3/SDAT P12.0
NOTE: The bold indicate a OTP pin name.
Figure 16-2. KS57P5532 Pin Assignments (64-QFP)
P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
16-3
KS57P5532 OTP
KS57C5532/P5532
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Pin Name Pin No. SDAT SCLK VPP (TEST) 28 (21) 29 (22) 30 (23) I/O I/O I I During Programming Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OTP is operating. Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
RESET
43 (36) 32 (25) / 64 (57)
I I
VDD/VSS
NOTE: Parentheses indicate pin number for 64 QFP package.
Table 16-2. Comparison of KS57P5532 and KS57C5532 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 1.8 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5V 64 SDIP/QFP User Program 1 time 64 SDIP/QFP Programmed at the factory KS57P5532 32 K byte EPROM KS57C5532 32 K byte mask ROM 1.8 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the KS57P5532, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5V 12.5V 12.5V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
16-4
KS57C5532/P5532
KS57P5532 OTP
Table 16-4. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI1 VO I OH I OL Conditions - All I/O ports - One I/O port active All I/O ports active Output Current Low One I/O port active Rating - 0.3 to 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15 (note) All I/O ports, total + 100 (Peak value) + 60 (note) Operating Temperature Storage Temperature TA Tstg - -
Duty . C C
Units V V V mA
mA
- 40 to + 85 - 65 to + 150
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 16-5. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 VIH4 Input Low Voltage VIL1 VIL2 VIL3 Conditions All input pins except those specified below for VIH2-VIH4 Ports 0, 1, 3, 6, 7, and RESET Ports 4 and 5 with pull-up resistors assigned XIN, XOUT and XTIN All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 3, 6, 7, and RESET XIN, XOUT and XTIN Min 0.7 VDD 0.8 VDD 0.7 VDD VDD - 0.1 - - Typ - Max VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 V Units V
16-5
KS57P5532 OTP
KS57C5532/P5532
Table 16-5. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output High Voltage Output Low Voltage Symbol VOH VOL1 Conditions IOH = - 1 mA Ports except 1 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4,5 only VDD = 2.0 to 5.5 V, IOL = 1.6mA VOL2 VDD = 4.5 V to 5.5 V IOL = 4mA all out Ports except ports 4,5 VDD = 2.0 to 5.5 V, IOL = 1.6mA Input High Leakage Current ILIH1 VI = VDD All input pins except those specified below for ILIH2 VI = VDD XIN, XOUT and XTIN Input Low Leakage Current ILIL1 VI = 0 V All input pins except below and RESET VI = 0 V XIN, XOUT and XTIN Output High Leakage Current Output Low Leakage Current Pull-up Resistor ILOH VO = VDD All output pins VO = 0 V All output pins VDD = 5 V; VI = 0 V except RESET VDD = 3 V RL3 VDD = 5 V; VI = 0 V; RESET VDD = 3 V
Pull-Down Resistor
Min VDD - 1.0 -
Typ - - -
Max - 2 0.4 2 0.4
Units V V V V V A
-
-
3
ILIH2
20
-
-
-3
A
ILIL2
- 20 A
-
-
3
ILOL
-
-
-3
RL1
25 50 100 200 25 50
45 89 212 441 46 95
100 200 400 800 100 200
k
RL4
VDD = 5 V ; VI = VDD; Port 12 VDD = 3 V
16-6
KS57C5532/P5532
KS57P5532 OTP
Table 16-5. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (DTMF ON) Conditions Run mode; VDD = 5.0 V 10% 3.58 MHz Crystal oscillator; C1 = C2 = 22 pF VDD = 3 V 10% IDD2 Run mode; VDD = 5.0 V 10% VDD = 3 V 10% IDD3 Idle mode; VDD = 5 V 10% VDD = 3 V 10% IDD4 IDD5 IDD6 Run mode; VDD = 3.0 V 10% 32 kHz Crystal oscillator Idle mode; VDD = 3.0 V 10% 32 kHz Crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Row Tone Level (2) Ratio of Column to Row Tone (2) Distortion (2) (Dual tone) VROW dBCR VDD = 2.0 V to 5.5 V RL =12 K; Temp = - 30 to 60 C VDD = 2.0 V to 5.5 V RL =12 K; Temp = - 30 to 60 C VDD = 2.0 V to 5.5 V 1 MHz band, RL = 12 K Temp = - 30 to 60 C SCMOD = 0000B XT = 0 V SCMOD = 0100B - 16 1 - 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz - 1.6 2.7 2.0 1.3 0.9 0.8 0.7 0.3 0.2 12.5 4.5 1.9 0.6 0.2 0.1 - 14 2 3.0 8.0 4.0 4.0 2.3 2.5 1.8 1.5 1.0 30 15 5 3 3 2 - 11 3 dBV dB A Min - Typ 3.0 Max 5.0 Units mA
(DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF
THD
-
-
5
%
NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. 3. DTMF electrical characteristics. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
16-7
KS57P5532 OTP
KS57C5532/P5532
Table 16-6. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter
Test Condition
Min 0.4
Typ -
Max 6.0
Units MHz
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator
XIN XOUT
0.4 - 0.4
- - -
3.0 4 6.0 ms MHz
VDD = 3 V
Oscillation frequency (1) VDD = 2.7 V to 5.5 V
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock
XIN XOUT
0.4 - 0.4
- - -
3.0 10 6.0 ms MHz
VDD = 3 V VDD = 2.7 V to 5.5 V
XIN input frequency (1)
VDD = 1.8 V to 5.5 V Xin input high and low level width (tXH, tXL) -
0.4 83.3
- -
3.0 1250 ns
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
16-8
KS57C5532/P5532
KS57P5532 OTP
Table 16-7. Recommended Oscillator Constants (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) Frequency Range Load Cap (pF) C1 TDK FCR FCR CCR M5 MC5 MC3 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
Table 16-8. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTI
N
Parameter Oscillation frequency (1)
Test Condition -
Min 32
Typ 32.76 8
Max 35
Units kHz
XTOUT
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V
- - 32
1.0 - -
2 10 100
s s kHz
External Clock
XTI XTOUT
N
XTIN input frequency (1)
-
XTIN input high and low level width (tXH, tXL)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is terminated.
16-9
KS57P5532 OTP
KS57C5532/P5532
Table 16-9. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
CPU Clock 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 0.75 MHz
4.2 MHz 3 MHz
15.625 kHz 1 2 1.8 3 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64) 4 5 6 7
Figure 16-3. Standard Operating Voltage Range
16-10

▲Up To Search▲

Price & Availability of KS57C5532

	To Download KS57C5532 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .